Configure 0 register of Tx channel0
| OUT_RST_CH0 | This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer. |
| OUT_LOOP_TEST_CH0 | reserved |
| OUT_AUTO_WRBACK_CH0 | Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. |
| OUT_EOF_MODE_CH0 | EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA |
| OUT_ETM_EN_CH0 | Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task. |
| OUT_BURST_SIZE_SEL_CH0 | 3’b000-3’b100:burst length 8byte~128byte |
| OUT_CMD_DISABLE_CH0 | 1:mean disable cmd of this ch0 |
| OUT_ECC_AEC_EN_CH0 | 1: mean access ecc or aes domain,0: mean not |
| OUTDSCR_BURST_EN_CH0 | Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM. |